The present invention relates generally to semiconductor devices, and more particularly to field-effect elements such as field-effect transistors (FET) and memory cells for use in random-access memory (RAM) integrated circuits.
The integrated circuit art strives for improvements in processing techniques for reducing the size of circuit elements and improving device yields. The present invention is directed to a number of related problems inherently involved in making high density RAMs.
In particular, it has been found that the formation of thick field oxide layers in selected areas of a substrate using prior art isoplanar techniques causes the undesirable transportation of silicon nitride into portions of the substrate from silicon nitride layers used to delineate the field oxide growth. The present invention provides steps which alleviate such nitride contamination of the substrate.
An aspect of prior art processes which limits the number of elements per unit area on a semiconductor chip is the use of deposited oxide as a mask for etching underlying layers. Deposited oxide tends to be lumpy and uneven in thickness, which hinders precise mask formation thereby affecting tolerances and limiting element density. The present invention overcomes the limitations of deposited oxide masks.
Additionally, a troublesome prior art problem solved by the present invention is lateral etching of oxide layers under polycrystalline silicon gate layers incident to opening diffusion windows to the device substrate. The resulting oxide undercut of such gate layers can cause device failure by a short circuit between a gate layer and the substrate. Prior art methods of depositing oxide to fill in the undercut have proved to be unreliable.
Another troublesome prior art problem solved by the present invention is extensive lateral etching of stabilization layer oxides incident to opening contact windows in devices which employ such stabilization layers. It has been a practice in the prior art to deposit a relatively thick layer of doped oxide over a relatively thin layer of essentially undoped thermally grown oxide for the known purpose of preventing contaminants such as sodium from migrating into the substrate. When contact windows are subsequently opened by etching through a photoresist mask, the doped oxide (i.e., the stabilization layer) etches laterally under the mask by a substantial amount by virtue of the disparity in etch rates of doped deposited oxide and undoped grown oxide. Doped deposited oxide (particularly the "low temperature" variety deposited at about 400.degree. C.) typically etches about ten times as fast as undoped grown oxide. Since the etch duration must be long enough to penetrate through the underlying grown oxide layer, the amount of lateral etch of the doped deposited oxide under the mask is typically somewhat greater than ten times the thickness of the undoped grown oxide. It will be appreciated tha whatever amount of planned overetching is included in the duration aggravates this problem. Clearly, the element density per unit of chip area is adversely affected by such extensive lateral etching. Process steps are provided in the present invention which substantially eliminate this problem.